1. Field of the Invention
The present invention relates to a phase change memory device and a method of manufacturing the same, and more particularly, to a phase change memory device, which is capable of ensuring low reset current, and to a method of manufacturing the same.
2. Description of the Related Art
Recently, a considerable amount of research into the developing novel memory devices that have simple configurations which are capable of accomplishing a high level of integration while retaining the characteristics of a non-volatile memory device has been undertaken. One novel memory device that promises to satisfy the above critiques is the phase change memory device.
The phase change memory device is a memory device in which, based on the particular phase of a phase change layer interposed between a lower electrode and an upper electrode, logical information can be stored in these cells. These phase change memory devices often exploit a physical property difference, i.e., a change in the electrical resistance across the phase change layer as a function of which particular phase the phase change memory is at. A presently preferred phase change material reversibly exhibits transitioning between an ordered crystalline solid state to a disordered amorphous solid state in which the ordered crystalline solid state usually exhibits a lower electrical resistance than the disordered amorphous solid state. One can apply heat via an electrical current (i.e., Joule heat) through these phase change materials to drive the phase change transitions.
Also another important criteria in the successful development of these phase change memory devices should take into consideration the reducing or minimizing the reset current needed to convert the phase change layer in the crystalline state into the phase change layer in the amorphous state.
A typical technique used to reduce the reset current of the phase change memory device is to design as small as possible the contact interface between a phase change material and an electrode. One way to do this is to simply reduce the size of the electrode. However, since these types of memory devices are also subjected to the same ever increasing demands for providing higher and higher integration devices then the size of phase change memory devices is also expected to decrease along with decreasing the electrode area. Therefore there exist real physical limitations on how small the electrode can be fabricated brought about by limitations such as the resolution constraints of photolithography. Thus there are real physical limits on how small the electrodes can be made. Consequently, it becomes more and more difficult to ensure low reset current in highly integrated phase change memory devices.
Another technique of reducing the reset current of the phase change memory device is to embed the phase change material within a hole. Specifically, a phase change layer is provided in an embedded form, namely, a confined form. This method is advantageous because phase change occurs sequestered in the center of a small hole, and thus reset current may be ensured to be lower than when a phase change layer is provided in a patterned form. However, this method is also problematic because there exist physical limitations on how small of a size of the hole can be fabricated due to high integration demands of memory devices. Therefore, embedding the phase change material within a hole also makes it difficult to ensure low reset currents in high integration demands of memory devices.